View MAX7034AUIVT_2049842.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max7034 fully integrated low-power cmos super- heterodyne receiver is ideal for receiving amplitude- shift-keyed (ask) data in the 300mhz to 450mhz frequency range (including the popular 315mhz and 433.92mhz frequencies). the receiver has an rf sensi- tivity of -114dbm. with few external components and a low-current power-down mode, it is ideal for cost-sensi- tive and power-sensitive applications typical in the automotive and consumer markets. the max7034 con- sists of a low-noise amplifier (lna), a fully differential image-rejection mixer, an on-chip phase-locked loop (pll) with integrated voltage-controlled oscillator (vco), a 10.7mhz if limiting amplifier stage with received-signal-strength indicator (rssi), and analog baseband data-recovery circuitry. the max7034 is available in a 28-pin (9.7mm x 4.4mm) tssop package and is specified over the automotive (-40c to +125c) temperature range. features optimized for 315mhz or 433.92mhz band operates from single +5.0v supply selectable image-rejection center frequency selectable x64 or x32 f lo /f xtal ratio low (< 6.7ma) operating supply current < 3.0 a low-current power-down mode for efficient power cycling 250 s startup time built-in 44db rf image rejection excellent receive sensitivity over temperature -40? to +125? operation max7034 315mhz/434mhz ask superheterodyne receiver ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 xtal2 shdn pdout dataout dsp en_reg dffb opp dsn dfo ifin2 ifin1 xtalsel dvdd dgnd mixout irsel agnd mixin2 mixin1 avdd lnaout agnd lnasrc lnain avdd v dd5 xtal1 tssop top view max7034 + pin configuration ordering information applications 19-3109; rev 2; 5/11 /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. typical application circuit appears at end of data sheet. part temp range pin-package max7034aui/v+t -40 c to +125 c 28 tssop automotive remote keyless entry security systems garage door openers home automation remote controls local telemetry wireless sensors
max7034 315mhz/434mhz ask superheterodyne receiver 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics ( typical application circuit , v dd5 = +4.5v to +5.5v, no rf signal applied. t a = -40c to +125c, unless otherwise noted. typical val- ues are at v dd5 = +5.0v and t a = +25c, unless otherwise noted.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd5 to agnd.......................................................-0.3v to +6.0v avdd to agnd .....................................................-0.3v to +4.0v dvdd to dgnd .....................................................-0.3v to +4.0v agnd to dgnd.....................................................-0.1v to +0.1v irsel, dataout, xtalsel, shdn , en_reg to agnd ....................-0.3v to (v dd5 + 0.3v) all other pins to agnd ..........................-0.3v to (v dvdd + 0.3v) continuous power dissipation (t a = +70c) 28-pin tssop (derate 12.8mw/c above +70c) ..1025.6mw operating temperature range .........................-40c to +125c storage temperature range .............................-65c to +150c junction temperature ......................................................+150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units supply voltage v dd5 +5.0v nominal supply voltage 4.5 5.0 5.5 v f rf = 315mhz 6.7 8.2 supply current i dd v shdn = v dd5 f rf = 434mhz 7.2 8.7 ma shutdown supply current i shdn v shdn = 0v 3 8 a input-voltage low v il 0.4 v en_reg, shdn v dd5 - 0.4 input-voltage high v ih xtalsel v d v dd - 0.4 v input logic current high i ih 15 a f rf = 434mhz, v irsel = v d v dd v d v dd - 0.4 f rf = 375mhz, v irsel = v d v dd /2 1.1 v d v dd - 1.5 image-reject select voltage (note 2) f rf = 315mhz, v irsel = 0v 0.4 v dataout output-voltage low v ol i sink = 10a 0.125 v dataout output-voltage high v oh i source = 10a v d d 5 - 0.125 v
max7034 315mhz/434mhz ask superheterodyne receiver _______________________________________________________________________________________ 3 ac electrical characteristics ( typical application circuit , v dd5 = +4.5v to +5.5v, all rf inputs are referenced to 50 ? , f rf = 433.92mhz, t a = -40c to +125c, unless otherwise noted. typical values are at v dd5 = +5.0v and t a = +25c.) (note 1) parameter symbol conditions min typ max units general characteristics startup time t on time for valid signal detection after v shdn = v dd5 . does not include baseband filter settling. 250 s receiver input frequency range f rf 300 450 mhz maximum receiver input level 0 dbm +25c, 315mhz -114 sensitivity at t a = +25 o c (note 3) +25c, 434mhz -113 dbm +125c, 315mhz -113 sensitivity at t a = +125c (note 3) +125c, 434mhz -110 dbm manchester coded 33 maximum data rate nrz coded 66 kbps lna/mixer lna/mixer voltage gain (note 4) 330 ? if filter load 45 db lna/mixer input-referred 1db compression point -50 dbm mixer output impedance z out_mix 330 ? f rf = 434mhz, v irsel = v dvdd 42 f rf = 375mhz, v irsel = v dvdd /2 44 mixer image rejection f rf = 315mhz, v irsel = 0v 44 db intermediate frequency (if) input impedance z in_if 330 ? operating frequency f if bandpass response 10.7 mhz 3db bandwidth 10 mhz rssi linearity 0.5 db rssi dynamic range 80 db p rfin < -120dbm 1.15 rssi level p rfin > -40dbm 2.2 v
max7034 315mhz/434mhz ask superheterodyne receiver 4 _______________________________________________________________________________________ note 1: 100% tested at t a = +125c. guaranteed by design and characterization over entire temperature range. note 2: irsel is internally set to 375mhz ir mode. it can be left open when the 375mhz image-rejection setting is desired. bypass to agnd with a 1nf capacitor in a noisy environment. note 3: peak power level. ber = 2 x 10 -3 , manchester encoded, data rate = 4kbps, if bandwidth = 280khz. note 4: the voltage conversion gain is measured with the lna input matching inductor and the lna/mixer resonator in place, and does not include the if filter insertion loss. note 5: crystal oscillator frequency for other rf carrier frequency within the 300mhz to 450mhz range is (f rf - 10.7mhz)/64 for xtalsel = 0v, and (f rf - 10.7mhz)/32 for xtalsel = v dvdd . parameter symbol conditions min typ max units data filter maximum bandwidth 50 khz data slicer comparator bandwidth 100 khz output high voltage v vdd5 v output low voltage 0v crystal oscillator v xtalsel = 0v 6.6128 f rf = 433.92mhz v xtalsel = v dvdd 13.2256 v xtalsel = 0v 4.7547 crystal frequency (note 5) f xtal f rf = 315mhz v xtalsel = v dvdd 9.5094 mhz crystal tolerance 50 ppm input capacitance from each pin to ground 6.2 pf maximum load capacitance c load 10 pf ac electrical characteristics (continued) ( typical application circuit , v dd5 = +4.5v to +5.5v, all rf inputs are referenced to 50 ? , f rf = 433.92mhz, t a = -40c to +125c, unless otherwise noted. typical values are at v dd5 = +5.0v and t a = +25c.) (note 1)
max7034 315mhz/434mhz ask superheterodyne receiver _______________________________________________________________________________________ 5 typical operating characteristics ( typical application circuit , v dd5 = +5.0v, f rf = 433.92mhz, t a = +25c, unless otherwise noted.) supply current vs. supply voltage supply voltage (v) supply current (ma) max7034 toc01 4.5 4.7 4.9 5.1 5.3 5.5 6.6 7.0 6.8 7.2 7.4 7.6 7.8 +105 c +125 c +85 c +25 c -40 c supply current vs. rf frequency rf frequency (mhz) supply current (ma) max7034 toc02 250 300 350 400 450 500 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 +105 c +125 c +85 c +25 c -40 c bit-error rate vs. peak rf input power peak rf input power (dbm) bit-error rate (%) max7034 toc03 -130 -125 -120 -115 -110 0.01 0.10 1.00 10.00 100.00 315mhz 433.92mhz sensitivity vs. temperature temperature ( c) sensitivity (dbm) max7034 toc04 -40 -15 10 35 60 85 110 -120 -118 -116 -114 -112 -110 -108 -106 -104 -102 433.92mhz 315mhz rssi vs. rf input power rf input power (dbm) rssi (v) max7034 toc05 -140 -120 -100 -80 -60 -40 -20 0 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 if bandwidth = 280khz rssi and delta vs. if input power if input power (dbm) rssi (v) delta max7034 toc06 -25 -20 -15 -10 -5 0 5 10 15 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 rssi delta lna/mixer voltage gain vs. if frequency if frequency (mhz) lna/mixer voltage gain (db) max7034 toc07 0 5 10 15 20 25 30 -5 5 15 25 35 45 55 65 upper sideband lower sideband 49.7db image rejection image rejection vs. rf frequency rf frequency (mhz) image rejection (db) max7034 toc08 280 300 320 340 360 380 400 420 440 460 480 0 10 20 30 40 50 60 f rf = 315mhz f rf = 433.92mhz image rejection vs. temperature temperature ( c) image rejection (db) max7034 toc09 -40 -15 10 35 60 85 110 40 42 44 46 48 50 52 433.92mhz 315mhz
pin description pin name function 1 xtal1 crystal input 1 2, 7 avdd positive analog supply voltage. for +5v operation, pin 2 is the output of an on-chip +3.4v low- dropout regulator, and should be bypassed to agnd with a 0.1f capacitor as close as possible to the pin. pin 7 must be externally connected to the supply from pin 2, and bypassed to agnd with a 0.01f capacitor as close as possible to the pin (see the voltage regulator section and the typical application circuit ). 3 lnain low-noise amplifier input. see the low-noise amplifier section. phase noise vs. offset frequency max7033 toc13 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k 100 -120 -100 -80 -60 -40 -20 0 -140 10 10m f rf = 315mhz phase noise vs. offset frequency max7033 toc14 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k 100 -120 -100 -80 -60 -40 -20 0 -140 10 10m f rf = 433.92mhz max7034 315mhz/434mhz ask superheterodyne receiver 6 _______________________________________________________________________________________ typical operating characteristics (continued) ( typical application circuit , v dd5 = +5.0v, f rf = 433.92mhz, t a = +25c, unless otherwise noted.) normalized if gain vs. if frequency max7034 toc10 if frequency (mhz) normalized if gain (db) 10 -25 -20 -15 -10 -5 0 5 -30 1100 s 11 magnitude plot of rfin vs. frequency max7034 toc11 frequency (mhz) s 11 magnitude (db) 470 440 380 410 260 290 320 350 230 -40 -30 -20 -10 0 10 20 30 40 50 -50 200 500 315mhz -24.1db s 11 smith chart plot of rfin max7034 toc12 500mhz 200mhz with input matching 315mhz
max7034 315mhz/434mhz ask superheterodyne receiver _______________________________________________________________________________________ 7 pin description (continued) pin name function 4 lnasrc low-noise amplifier source for external inductive degeneration. connect inductor to ground to set lna input impedance. see the low-noise amplifier section. 5, 10 agnd analog ground 6 lnaout low-noise amplifier output. connect to mixer input through an lc tank filter. see the low-noise amplifier section. 8 mixin1 1st differential mixer input. connect to lc tank filter from lnaout through a 100pf capacitor. see the typical application circuit. 9 mixin2 2nd differential mixer input. connect to v dd3 side of the lc tank filter through a 100pf capacitor. see the typical application circuit. 11 irsel image-rejection select. set v irsel = 0v to center image rejection at 315mhz. leave irsel unconnected to center image rejection at 375mhz. set v irsel = dvdd to center image rejection at 434mhz. see the mixer section. 12 mixout 330 ? mixer output. connect to the input of the 10.7mhz bandpass filter. 13 dgnd digital ground 14 dvdd positive digital supply voltage. connect to both of the avdd pins. bypass to dgnd with a 0.01f capacitor as close as possible to the pin (see the typical application circuit ). 15 en_reg regulator enable. connect to v dd5 to enable internal regulator. pull this pin low to allow device operation between +3.0v and +3.6v. see the voltage regulator section. 16 xtalsel crystal divider ratio select. drive xtalsel low to select f lo /f xtal ratio of 64, or drive xtalsel high to select f lo /f xtal ratio of 32. 17 ifin1 1st differential intermediate-frequency limiter amplifier input. connect to the output of a 10.7mhz bandpass filter. 18 ifin2 2nd differential intermediate-frequency limiter amplifier input. bypass to agnd with a 1500pf capacitor as close as possible to the pin. 19 dfo data filter output 20 dsn negative data slicer input 21 opp noninverting op-amp input for the sallen-key data filter 22 dffb data filter feedback node. input for the feedback of the sallen-key data filter. 23 dsp positive data slicer input 24 v dd5 +5v supply voltage. bypass to agnd with a 0.01f capacitor as close as possible to the pin. for +5v operation, v dd5 is the input to an on-chip voltage regulator whose +3.4v output appears at avdd pin 2. (see the voltage regulator section and the typical application circuit ). 25 dataout digital baseband data output 26 pdout peak-detector output 27 shdn power-down select input. drive high to power up the ic. internally pulled down to agnd with a 100k ? resistor. 28 xtal2 c r ystal inp ut 2. c an al so b e d r i ven w i th an exter nal r efer ence osci l l ator . s ee the c r ystal o sci l l ator secti on.
max7034 315mhz/434mhz ask superheterodyne receiver 8 _______________________________________________________________________________________ functional diagram lnaout mixin1 mixin2 0? 90? ifin1 mixout ifin2 rssi r df2 100k ? r df1 100k ? divide by 64 vco loop filter phase detector crystal driver power- down if limiting amps 7 lnasrc data slicer data filter q i image rejection 3.4v reg 24 2 irsel 13 5, 10 avdd v dd5 avdd dvdd dgnd agnd lnain 3 xtalsel 16 xtal1 1 xtal2 28 shdn 27 dataout 25 dsn 20 dsp 23 dfo 19 pdout 26 opp 21 dffb 22 4 15 6 8 9 11 12 17 18 en_reg 2 1 max7034 lna 14 detailed description the max7034 cmos superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. depending on signal power and component selection, data rates can be as high as 33kbps manchester (66kbps nrz). the max7034 is designed to receive binary ask data modulated in the 300mhz to 450mhz frequency range. ask modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. voltage regulator for operation with a single +4.5v to +5.5v supply voltage, connect v dd5 and the en_reg pin to the supply voltage. an on-chip voltage regulator drives one of the avdd pins (pin 2) to approximately +3.4v. for proper operation, dvdd and both avdd pins must be connected together. for operation with a single +3.0v to +3.6v supply voltage, connect both the avdd pins, dvdd, and v dd5 to the supply voltage and connect the en_reg pin to ground (which disables the internal voltage regulator). if the max7034 is powered from +3.0v to +3.6v, the perfor- mance is limited to the -40c to +105c range. in either supply voltage mode, bypass v dd5 , dvdd, and the pin 7 avdd pin to agnd with 0.01f capacitors, and the pin 2 avdd to agnd with a 0.1f capacitor, all placed as close as possible to the pins. low-noise amplifier the lna is an nmos cascode amplifier with off-chip inductive degeneration. the gain and noise figures are dependent on both the antenna matching network at the lna input and the lc tank network between the lna output and the mixer inputs. the off-chip inductive degeneration is achieved by connecting an inductor from lnasrc to agnd. this inductor sets the real part of the input impedance at lnain, allowing for a more flexible input impedance match, such as a typical printed-circuit board (pcb) trace antenna. a nominal value for this inductor with a 50 ? input impedance is 15nh, but is affected by the pcb trace. the lc tank filter connected to lnaout comprises l1 and c9 (see the typical application circuit ). select l1 and c9 to resonate at the desired rf input frequency. the resonant frequency is given by: where: l total = l1 + l parasitics . c total = c9 + c parasitics . f lc rf total total = 1 2
max7034 315mhz/434mhz ask superheterodyne receiver _______________________________________________________________________________________ 9 l parasitics and c parasitics include inductance and capacitance of the pcb traces, package pins, mixer input impedance, etc. these parasitics at high frequen- cies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. the total parasitic capacitance is generally between 4pf and 6pf. mixer a unique feature of the max7034 is the integrated image rejection of the mixer. this device eliminates the need for a costly front-end saw filter for most applica- tions. advantages of not using a saw filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. the mixer cell is a pair of double balanced mixers that perform an iq downconversion of the rf input to the 10.7mhz if from a low-side injected lo (i.e., f lo = f rf - f if ). the image-rejection circuit then combines these signals to achieve 44db of image rejection. low-side injection is required due to the on-chip image-rejection architecture. the if output is driven by a source follow- er biased to create a driving-point impedance of 330 ? ; this provides a good match to the off-chip 330 ? ceram- ic if filter. the irsel pin is a logic input that selects one of the three possible image-rejection frequencies. when v irsel = 0v, the image rejection is tuned to 315mhz. v irsel = v dvdd /2 tunes the image rejection to 375mhz, and v irsel = v dvdd tunes the image rejection to 434mhz. the irsel pin is internally set to v dvdd /2 (image rejec- tion at 375mhz) when it is left unconnected, thereby eliminating the need for an external v dvdd /2 voltage. phase-locked loop the pll block contains a phase detector, charge pump, integrated loop filter, vco, asynchronous 64x clock divider, and crystal oscillator driver. besides the crystal, this pll does not require any external compo- nents. the vco generates a low-side lo. the relation- ship between the rf, if, and crystal frequencies is given by: where: m = 1 (v xtalsel = v dvdd ) or 2 (v xtalsel = 0v) to allow the smallest possible if bandwidth (for best sen- sitivity), minimize the tolerance of the reference crystal. intermediate frequency and rssi the if section presents a differential 330 ? load to pro- vide matching for the off-chip ceramic filter. the six internal ac-coupled limiting amplifiers produce an overall gain of approximately 65db, with a bandpass- filter-type response centered near the 10.7mhz if fre- quency with a 3db bandwidth of approximately 10mhz. the rssi circuit demodulates the if by producing a dc output proportional to the log of the if signal level, with a slope of approximately 14.2mv/db. applications information crystal oscillator the crystal oscillator in the max7034 is designed to present a capacitance of approximately 3pf between the xtal1 and xtal2. if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its intended operating frequency, introducing an error in the reference frequency. crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. for example, a 4.7547mhz crystal designed to operate with a 10pf load capacitance oscillates at 4.7563mhz with the max7034, causing the receiver to be tuned to 315.1mhz rather than 315.0mhz, an error of about 100khz, or 320ppm. it is very important to use a crystal with a load capacitance that is equal to the capacitance of the max7034 crystal oscillator plus pcb parasitics. in actuality, the oscillator pulls every crystal. the crys- tals natural frequency is really below its specified fre- quency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded as specified (i.e., c load = c spec ), the frequency pulling equals zero. f c cccc p m case load case spec = ++ ? ? ? ? ? ? 2 11 10 6 - f ff m xtal rf if = - 32
it is possible to use an external reference oscillator in place of a crystal to drive the vco. ac-couple the exter- nal oscillator to xtal2 with a 1000pf capacitor. drive xtal2 with a signal level of approximately 500mv p-p . ac-couple xtal1 to ground with a 1000pf capacitor. data filter the data filter is implemented as a 2nd-order lowpass sallen-key filter. the pole locations are set by the com- bination of two on-chip resistors and two external capacitors. adjusting the value of the external capaci- tors changes the corner frequency to optimize for differ- ent data rates. the corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. the configuration shown in figure 1 can create a butterworth or bessel response. the butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works well for filtering digital data. to calculate the value of c5 and c6, use the following equations, along with the coefficients in table 1: where f c is the desired 3db corner frequency. for example, to choose a butterworth filter response with a corner frequency of 5khz: choosing standard capacitor values changes c5 to 470pf and c6 to 220pf, as shown in the typical application circuit . data slicer the data slicer takes the analog output of the data filter and converts it to a digital signal. this is achieved by using a comparator and comparing the analog input to a threshold voltage. one input is supplied by the data filter output. both comparator inputs are accessible off- chip to allow for different methods of generating the slicing threshold, which is applied to the second com- parator input. the suggested data slicer configuration uses a resistor (r1) connected between dsn and dsp with a capaci- tor (c4) from dsn to dgnd (figure 2). this configura- tion averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the values of r1 and c4 affect how fast the threshold tracks to the analog ampli- tude. be sure to keep the corner frequency of the rc circuit much lower than the lowest expected data rate. note that a long string of zeros or ones can cause the threshold to drift. this configuration works best if a cod- ing scheme, such as manchester coding, which has an equal number of zeros and ones, is used. to prevent continuous toggling of dataout in the absence of an rf signal due to noise, add hysteresis to the data slicer as shown in figure 3. c k khz pf c k khz pf 5 1 000 1 414 100 3 14 5 450 6 1 414 4 100 3 14 5 225 . .. . . = ()( )()() = ()( )( )( ) ? ? c b akf c a kf c c 5 100 6 4 100 = ()()() = ()()() max7034 315mhz/434mhz ask superheterodyne receiver 10 ______________________________________________________________________________________ rssi r df1 100k ? r df2 100k ? c5 19 dfo 21 opp 22 dffb c6 max7034 filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618 figure 1. sallen-key lowpass data filter table 1. coefficents to calculate c5 and c6
peak detector the peak-detector output (pdout), in conjunction with an external rc filter, creates a dc output voltage equal to the peak value of the data signal. the resistor pro- vides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. for faster data slicer response, use the circuit shown in figure 4. for more details on hysteresis and peak-detector applications, refer to maxim application note 3671, data slicing techniques for uhf ask receivers . layout considerations a properly designed pcb is an essential part of any rf/microwave circuit. on high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. at high frequencies, trace lengths that are on the order of /10 or longer act as antennas. keeping the traces short also reduces parasitic induc- tance. generally, 1 inch of a pcb trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5 inch trace connecting a 100nh inductor adds an extra 10nh of inductance or 10%. to reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. also, use low-inductance connections to ground on all gnd pins, and place decoupling capacitors close to all power-supply pins. control interface considerations when operating the max7034 with a +4.5v to +5.5v supply voltage, the shdn pin can be driven by a microcontroller with either +3.0v or +5v interface logic levels. when operating the max7034 with a +3.0v to +3.6v supply, only +3.0v logic from the microcontroller is allowed. max7034 315mhz/434mhz ask superheterodyne receiver ______________________________________________________________________________________ 11 data slicer r1 25 dataout 20 dsn 19 dfo 23 dsp c4 max7034 data slicer r3 r1 r2 r4 25 dataout *optional 23 dsp 19 dfo 20 dsn c4 max7034 figure 3. generating data slicer hysteresis data slicer 25k ? 25 dataout 20 dsn 19 dfo 26 pdout 23 dsp max7034 47nf figure 4. using pdout for faster startup figure 2. generating data slicer threshold
max7034 315mhz/434mhz ask superheterodyne receiver 12 ______________________________________________________________________________________ typical application circuit xtal1 r2 r3 to/from p power-down data out avdd lnain lnasrc agnd avdd mixin1 mixin2 agnd irsel mixout dgnd dvdd y1 if filter component values in table 2 ***see the mixer section. *see the phase-locked loop section. **see the voltage regulator section. gnd in out * ** *** c5 c10 c9 c4 c3 c2 c1 c11 c12 c15 c7 r1 c13 rf input l3 l2 l1 v dd3 v dd3 if v dd is 3.0v to 3.6v 4.5v to 5.5v created by ldo, available at avdd (pin 2) connected to v dd connected to v dd grounded then v dd3 is and en_reg is x1 (see table) v dd v dd c14 c6 c8 en_reg xtalsel ifin1 ifin2 dfo dsn opp dffb dsp dataout pdout shdn xtal2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v dd5 lnaout max7034
max7034 315mhz/434mhz ask superheterodyne receiver ______________________________________________________________________________________ 13 chip information process: cmos component value for value for description c1 100pf 100pf 5% c2 open open 0.1pf c3 100pf 100pf 5% c4 100pf 100pf 5% c5 1500pf 1500pf 10% c6 220pf 220pf 5% c7 470pf 470pf 5% c8 0.47f 0.47f 20% c9 220pf 220pf 10% c10 0.01f 0.01f 20% c11 0.1f 0.1f 20% c12 100pf 100pf 5% c13 100pf 100pf 5% c14 0.01f 0.01f 20% c15 0.01f 0.01f 20% l1 56nh 120nh murata lqp11a l2 15nh 15nh murata lqp11a l3 27nh 51nh murata lqp11a r1 5.1k ? 5.1k ? 5% r2 open open r3 0 ? 0 ? x1 ( 64) 6.6128mhz* 4.7547mhz* ndk or suntsu x1 ( 32) 13.2256mhz* 9.5094mhz* ndk or suntsu y1 10.7mhz ceramic filter 10.7mhz ceramic filter murata table 2. component values for typical application circuit package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tssop u28+1 21-0066 90-0171 * crystal frequencies shown are for 64 (v xtalsel = 0v) and 32 (v xtalsel = v dd ).
max7034 315mhz/434mhz ask superheterodyne receiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/08 initial release 1 3/09 added /v designation to part number. 1 2 5/11 updated pin description , functional diagram , voltage regulator section, typical application circuit , and package information ; added control interface considerations section 7, 8, 11, 12, 13

▲Up To Search▲

Price & Availability of MAX7034AUIVT

	To Download MAX7034AUIVT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .